Symbol: regUVD_SUVD_CGC_STATUS_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
1255
#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_offset.h
371
#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h
373
#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_offset.h
354
#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
351
#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h
612
#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1