Symbol: regUVD_MPC_SET_MUXA1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
1044
#define regUVD_MPC_SET_MUXA1 0x02cf
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_offset.h
460
#define regUVD_MPC_SET_MUXA1 0x01d7
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h
462
#define regUVD_MPC_SET_MUXA1 0x01d7
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_offset.h
443
#define regUVD_MPC_SET_MUXA1 0x01d7