Symbol: regUVD_MPC_SET_ALU_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
1053
#define regUVD_MPC_SET_ALU_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_offset.h
469
#define regUVD_MPC_SET_ALU_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h
471
#define regUVD_MPC_SET_ALU_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_offset.h
452
#define regUVD_MPC_SET_ALU_BASE_IDX 1