Symbol: regUVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h
1686
#define regUVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h
1198
#define regUVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1