Symbol: regUVD_DPG_LMA_MASK_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
1085
#define regUVD_DPG_LMA_MASK_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_offset.h
1165
#define regUVD_DPG_LMA_MASK_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h
1096
#define regUVD_DPG_LMA_MASK_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_offset.h
1138
#define regUVD_DPG_LMA_MASK_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
965
#define regUVD_DPG_LMA_MASK_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h
100
#define regUVD_DPG_LMA_MASK_BASE_IDX 1