Symbol: regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
1739
#define regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
1751
#define regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX 1