Symbol: regSDMA0_QUEUE0_RB_WPTR_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
201
#define regSDMA0_QUEUE0_RB_WPTR_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
207
#define regSDMA0_QUEUE0_RB_WPTR_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
206
#define regSDMA0_QUEUE0_RB_WPTR_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
193
#define regSDMA0_QUEUE0_RB_WPTR_BASE_IDX 0