Symbol: regRLC_SPM_INT_STATUS_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
10583
#define regRLC_SPM_INT_STATUS_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
11203
#define regRLC_SPM_INT_STATUS_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
9014
#define regRLC_SPM_INT_STATUS_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
7024
#define regRLC_SPM_INT_STATUS_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
6913
#define regRLC_SPM_INT_STATUS_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
5051
#define regRLC_SPM_INT_STATUS_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
6565
#define regRLC_SPM_INT_STATUS_BASE_IDX 1