Symbol: regRLC_RLCV_TIMER_STAT_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
10737
#define regRLC_RLCV_TIMER_STAT_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
10031
#define regRLC_RLCV_TIMER_STAT_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
3467
#define regRLC_RLCV_TIMER_STAT_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
7151
#define regRLC_RLCV_TIMER_STAT_BASE_IDX 1