drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_0_offset.h

280

#define regMP1_SMN_C2PMSG_80_BASE_IDX 0

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h

336

#define regMP1_SMN_C2PMSG_80_BASE_IDX 0

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h

329

#define regMP1_SMN_C2PMSG_80_BASE_IDX 1

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_offset.h

282

#define regMP1_SMN_C2PMSG_80_BASE_IDX 0

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_offset.h

281

#define regMP1_SMN_C2PMSG_80_BASE_IDX 0

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_8_offset.h

283

#define regMP1_SMN_C2PMSG_80_BASE_IDX 0

drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h

190

#define regMP1_SMN_C2PMSG_80_BASE_IDX 0

drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_2_offset.h

190

#define regMP1_SMN_C2PMSG_80_BASE_IDX 1

drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h

267

#define regMP1_SMN_C2PMSG_80_BASE_IDX 1

drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_offset.h

191

#define regMP1_SMN_C2PMSG_80_BASE_IDX 2