drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_0_offset.h

248

#define regMP1_SMN_C2PMSG_64_BASE_IDX 0

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h

304

#define regMP1_SMN_C2PMSG_64_BASE_IDX 0

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h

297

#define regMP1_SMN_C2PMSG_64_BASE_IDX 1

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_offset.h

250

#define regMP1_SMN_C2PMSG_64_BASE_IDX 0

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_offset.h

249

#define regMP1_SMN_C2PMSG_64_BASE_IDX 0

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_8_offset.h

251

#define regMP1_SMN_C2PMSG_64_BASE_IDX 0

drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h

158

#define regMP1_SMN_C2PMSG_64_BASE_IDX 0

drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_2_offset.h

158

#define regMP1_SMN_C2PMSG_64_BASE_IDX 1

drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h

235

#define regMP1_SMN_C2PMSG_64_BASE_IDX 1

drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_offset.h

159

#define regMP1_SMN_C2PMSG_64_BASE_IDX 2