drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_0_offset.h

219

#define regMP1_SMN_C2PMSG_50 0x0272

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h

275

#define regMP1_SMN_C2PMSG_50 0x0272

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h

268

#define regMP1_SMN_C2PMSG_50 0x0272

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_offset.h

221

#define regMP1_SMN_C2PMSG_50 0x0272

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_offset.h

220

#define regMP1_SMN_C2PMSG_50 0x0272

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_8_offset.h

222

#define regMP1_SMN_C2PMSG_50 0x0272

drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h

129

#define regMP1_SMN_C2PMSG_50 0x0272

drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_2_offset.h

129

#define regMP1_SMN_C2PMSG_50 0x0072

drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h

206

#define regMP1_SMN_C2PMSG_50 0x0072

drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_offset.h

130

#define regMP1_SMN_C2PMSG_50 0x0072