drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h

2590

#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h

3483

#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h

2349

#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h

2810

#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h

2153

#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h

2153

#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h

3274

#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_offset.h

3253

#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h

2387

#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h

4814

#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_1_offset.h

2780

#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2