Symbol: regGCEA_SDP_VCC_RESERVE1_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
2537
#define regGCEA_SDP_VCC_RESERVE1_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
2649
#define regGCEA_SDP_VCC_RESERVE1_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
1658
#define regGCEA_SDP_VCC_RESERVE1_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
1289
#define regGCEA_SDP_VCC_RESERVE1_BASE_IDX 0