Symbol: regUVD_RB_BASE_HI3
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
1334
#define regUVD_RB_BASE_HI3 0x00b5
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_offset.h
220
#define regUVD_RB_BASE_HI3 0x00f5
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h
220
#define regUVD_RB_BASE_HI3 0x00f5
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_offset.h
207
#define regUVD_RB_BASE_HI3 0x00f5
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
198
#define regUVD_RB_BASE_HI3 0x0135
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h
459
#define regUVD_RB_BASE_HI3 0x0135