Symbol: regUVD_MPC_SET_MUXA0
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
1042
#define regUVD_MPC_SET_MUXA0 0x02ce
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_offset.h
458
#define regUVD_MPC_SET_MUXA0 0x01d6
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h
460
#define regUVD_MPC_SET_MUXA0 0x01d6
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_offset.h
441
#define regUVD_MPC_SET_MUXA0 0x01d6