Symbol: regCP_HQD_HQ_CONTROL1_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
4677
#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
4901
#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
3650
#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
3917
#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
3861
#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
770
#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
3359
#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0