Symbol: regCP_HQD_GFX_CONTROL_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
4453
#define regCP_HQD_GFX_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
4677
#define regCP_HQD_GFX_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
3426
#define regCP_HQD_GFX_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
3733
#define regCP_HQD_GFX_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
3665
#define regCP_HQD_GFX_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
680
#define regCP_HQD_GFX_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
3269
#define regCP_HQD_GFX_CONTROL_BASE_IDX 0