Symbol: regCP_HQD_EOP_CONTROL_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
4683
#define regCP_HQD_EOP_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
4907
#define regCP_HQD_EOP_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
3656
#define regCP_HQD_EOP_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
3923
#define regCP_HQD_EOP_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
3867
#define regCP_HQD_EOP_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
776
#define regCP_HQD_EOP_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
3365
#define regCP_HQD_EOP_CONTROL_BASE_IDX 0