Symbol: regCPG_UTCL1_STATUS_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
4541
#define regCPG_UTCL1_STATUS_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
4765
#define regCPG_UTCL1_STATUS_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
3514
#define regCPG_UTCL1_STATUS_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
3821
#define regCPG_UTCL1_STATUS_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
3765
#define regCPG_UTCL1_STATUS_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
664
#define regCPG_UTCL1_STATUS_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
3131
#define regCPG_UTCL1_STATUS_BASE_IDX 0