Symbol: regSDMA0_UTCL1_WR_STATUS
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
108
#define regSDMA0_UTCL1_WR_STATUS 0x0041
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
108
#define regSDMA0_UTCL1_WR_STATUS 0x0041
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
110
#define regSDMA0_UTCL1_WR_STATUS 0x0041
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
102
#define regSDMA0_UTCL1_WR_STATUS 0x0042
drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_offset.h
111
#define regSDMA0_UTCL1_WR_STATUS 0x003f