Symbol: regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
242
#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x00b2
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
248
#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x00b2
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
247
#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x00b2
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
232
#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x0099