Symbol: regSDMA0_QUEUE0_MIDCMD_DATA0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
252
#define regSDMA0_QUEUE0_MIDCMD_DATA0 0x00c0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
258
#define regSDMA0_QUEUE0_MIDCMD_DATA0 0x00c0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
257
#define regSDMA0_QUEUE0_MIDCMD_DATA0 0x00c0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
242
#define regSDMA0_QUEUE0_MIDCMD_DATA0 0x00a0