Symbol: regSDMA0_QUEUE0_MIDCMD_CNTL
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
274
#define regSDMA0_QUEUE0_MIDCMD_CNTL 0x00cb
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
280
#define regSDMA0_QUEUE0_MIDCMD_CNTL 0x00cb
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
279
#define regSDMA0_QUEUE0_MIDCMD_CNTL 0x00cb
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
240
#define regSDMA0_QUEUE0_MIDCMD_CNTL 0x009f