Symbol: regRLC_UTCL1_STATUS
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
10054
#define regRLC_UTCL1_STATUS 0x4cd4
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
10656
#define regRLC_UTCL1_STATUS 0x4cd4
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
8719
#define regRLC_UTCL1_STATUS 0x4cd4
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
6548
#define regRLC_UTCL1_STATUS 0x4cd4
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
6346
#define regRLC_UTCL1_STATUS 0x4cd4
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
5198
#define regRLC_UTCL1_STATUS 0x4cd4
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
6720
#define regRLC_UTCL1_STATUS 0x4cd4