drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_0_offset.h

379

#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h

387

#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h

380

#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_offset.h

381

#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_offset.h

380

#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_8_offset.h

382

#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3

drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h

289

#define regMP1_SMN_IH_SW_INT_CTRL 0x0342

drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_2_offset.h

289

#define regMP1_SMN_IH_SW_INT_CTRL 0x0142

drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h

366

#define regMP1_SMN_IH_SW_INT_CTRL 0x0142

drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_offset.h

386

#define regMP1_SMN_IH_SW_INT_CTRL 0x0142