drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_0_offset.h

377

#define regMP1_SMN_IH_SW_INT 0x02c2

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h

385

#define regMP1_SMN_IH_SW_INT 0x02c2

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h

378

#define regMP1_SMN_IH_SW_INT 0x02c2

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_offset.h

379

#define regMP1_SMN_IH_SW_INT 0x02c2

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_offset.h

378

#define regMP1_SMN_IH_SW_INT 0x02c2

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_8_offset.h

380

#define regMP1_SMN_IH_SW_INT 0x02c2

drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h

287

#define regMP1_SMN_IH_SW_INT 0x0341

drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_2_offset.h

287

#define regMP1_SMN_IH_SW_INT 0x0141

drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h

364

#define regMP1_SMN_IH_SW_INT 0x0141

drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_offset.h

384

#define regMP1_SMN_IH_SW_INT 0x0141