Symbol: regCP_HQD_WG_STATE_OFFSET
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
4700
#define regCP_HQD_WG_STATE_OFFSET 0x1fd9
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
4924
#define regCP_HQD_WG_STATE_OFFSET 0x1fd9
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
3673
#define regCP_HQD_WG_STATE_OFFSET 0x1fd9
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
3940
#define regCP_HQD_WG_STATE_OFFSET 0x1fd9
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
3884
#define regCP_HQD_WG_STATE_OFFSET 0x1fd9
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
793
#define regCP_HQD_WG_STATE_OFFSET 0x1275
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
3382
#define regCP_HQD_WG_STATE_OFFSET 0x1275