Symbol: mmUVD_GPCOM_VCPU_CMD_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h
55
#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
139
#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h
811
#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
512
#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h
828
#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1