drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

1468

#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x07a8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

1514

#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x0790

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h

390

#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h

359

#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h

470

#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h

568

#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788

drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h

470

#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8

drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h

470

#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x0190

drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h

466

#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8