drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h

6025

#define mmVGA_HDP_CONTROL 0xca

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h

6102

#define mmVGA_HDP_CONTROL 0xca

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h

7776

#define mmVGA_HDP_CONTROL 0xca

drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h

570

#define mmVGA_HDP_CONTROL 0x000a

drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h

4390

#define mmVGA_HDP_CONTROL 0x00CA

drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h

5142

#define mmVGA_HDP_CONTROL 0xca

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h

404

#define mmVGA_HDP_CONTROL 0x000a

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h

48

#define mmVGA_HDP_CONTROL 0x000a

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h

108

#define mmVGA_HDP_CONTROL 0x000a

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h

30

#define mmVGA_HDP_CONTROL 0x000a

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h

164

#define mmVGA_HDP_CONTROL 0x000a

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h

48

#define mmVGA_HDP_CONTROL 0x000a

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h

33

#define mmVGA_HDP_CONTROL 0x000a