drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

67

#define mmUVD_VCPU_CACHE_SIZE2 0x3d87

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

93

#define mmUVD_VCPU_CACHE_SIZE2 0x3D3B

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

65

#define mmUVD_VCPU_CACHE_SIZE2 0x3d87

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

71

#define mmUVD_VCPU_CACHE_SIZE2 0x3d87

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

87

#define mmUVD_VCPU_CACHE_SIZE2 0x3d87

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

188

#define mmUVD_VCPU_CACHE_SIZE2 0x0587

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

374

#define mmUVD_VCPU_CACHE_SIZE2 0x0587

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

624

#define mmUVD_VCPU_CACHE_SIZE2 0x0247

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

695

#define mmUVD_VCPU_CACHE_SIZE2 0x0145

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1071

#define mmUVD_VCPU_CACHE_SIZE2 0x0145