drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

65

#define mmUVD_VCPU_CACHE_SIZE1 0x3d85

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

92

#define mmUVD_VCPU_CACHE_SIZE1 0x3D39

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

63

#define mmUVD_VCPU_CACHE_SIZE1 0x3d85

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

69

#define mmUVD_VCPU_CACHE_SIZE1 0x3d85

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

85

#define mmUVD_VCPU_CACHE_SIZE1 0x3d85

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

184

#define mmUVD_VCPU_CACHE_SIZE1 0x0585

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

370

#define mmUVD_VCPU_CACHE_SIZE1 0x0585

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

620

#define mmUVD_VCPU_CACHE_SIZE1 0x0245

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

691

#define mmUVD_VCPU_CACHE_SIZE1 0x0143

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1067

#define mmUVD_VCPU_CACHE_SIZE1 0x0143