drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

63

#define mmUVD_VCPU_CACHE_SIZE0 0x3d83

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

91

#define mmUVD_VCPU_CACHE_SIZE0 0x3D37

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

61

#define mmUVD_VCPU_CACHE_SIZE0 0x3d83

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

67

#define mmUVD_VCPU_CACHE_SIZE0 0x3d83

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

83

#define mmUVD_VCPU_CACHE_SIZE0 0x3d83

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

180

#define mmUVD_VCPU_CACHE_SIZE0 0x0583

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

366

#define mmUVD_VCPU_CACHE_SIZE0 0x0583

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

616

#define mmUVD_VCPU_CACHE_SIZE0 0x0243

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

687

#define mmUVD_VCPU_CACHE_SIZE0 0x0141

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1063

#define mmUVD_VCPU_CACHE_SIZE0 0x0141