Symbol: mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h
179
#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
365
#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h
615
#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
686
#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h
1062
#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1