drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

64

#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

89

#define mmUVD_VCPU_CACHE_OFFSET1 0x3D38

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

62

#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

68

#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

84

#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

182

#define mmUVD_VCPU_CACHE_OFFSET1 0x0584

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

368

#define mmUVD_VCPU_CACHE_OFFSET1 0x0584

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

618

#define mmUVD_VCPU_CACHE_OFFSET1 0x0244

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

689

#define mmUVD_VCPU_CACHE_OFFSET1 0x0142

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1065

#define mmUVD_VCPU_CACHE_OFFSET1 0x0142