drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

62

#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

88

#define mmUVD_VCPU_CACHE_OFFSET0 0x3D36

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

60

#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

66

#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

82

#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

178

#define mmUVD_VCPU_CACHE_OFFSET0 0x0582

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

364

#define mmUVD_VCPU_CACHE_OFFSET0 0x0582

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

614

#define mmUVD_VCPU_CACHE_OFFSET0 0x0242

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

685

#define mmUVD_VCPU_CACHE_OFFSET0 0x0140

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1061

#define mmUVD_VCPU_CACHE_OFFSET0 0x0140