drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

75

#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

74

#define mmUVD_RBC_RB_WPTR_CNTL 0x3DA6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

73

#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

79

#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

95

#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

202

#define mmUVD_RBC_RB_WPTR_CNTL 0x05a6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

388

#define mmUVD_RBC_RB_WPTR_CNTL 0x05a6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

684

#define mmUVD_RBC_RB_WPTR_CNTL 0x0266

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

797

#define mmUVD_RBC_RB_WPTR_CNTL 0x02e6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1183

#define mmUVD_RBC_RB_WPTR_CNTL 0x02e6