drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

74

#define mmUVD_RBC_RB_WPTR 0x3da5

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

73

#define mmUVD_RBC_RB_WPTR 0x3DA5

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

72

#define mmUVD_RBC_RB_WPTR 0x3da5

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

78

#define mmUVD_RBC_RB_WPTR 0x3da5

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

94

#define mmUVD_RBC_RB_WPTR 0x3da5

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

200

#define mmUVD_RBC_RB_WPTR 0x05a5

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

386

#define mmUVD_RBC_RB_WPTR 0x05a5

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

682

#define mmUVD_RBC_RB_WPTR 0x0265

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

791

#define mmUVD_RBC_RB_WPTR 0x02e1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1175

#define mmUVD_RBC_RB_WPTR 0x02e1