drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

77

#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

72

#define mmUVD_RBC_RB_RPTR_ADDR 0x3DAA

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

75

#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

81

#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

97

#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

206

#define mmUVD_RBC_RB_RPTR_ADDR 0x05aa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

392

#define mmUVD_RBC_RB_RPTR_ADDR 0x05aa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

692

#define mmUVD_RBC_RB_RPTR_ADDR 0x026a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

787

#define mmUVD_RBC_RB_RPTR_ADDR 0x02df

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1171

#define mmUVD_RBC_RB_RPTR_ADDR 0x02df