drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

73

#define mmUVD_RBC_RB_RPTR 0x3da4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

71

#define mmUVD_RBC_RB_RPTR 0x3DA4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

71

#define mmUVD_RBC_RB_RPTR 0x3da4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

77

#define mmUVD_RBC_RB_RPTR 0x3da4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

93

#define mmUVD_RBC_RB_RPTR 0x3da4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

198

#define mmUVD_RBC_RB_RPTR 0x05a4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

384

#define mmUVD_RBC_RB_RPTR 0x05a4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

680

#define mmUVD_RBC_RB_RPTR 0x0264

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

789

#define mmUVD_RBC_RB_RPTR 0x02e0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1173

#define mmUVD_RBC_RB_RPTR 0x02e0