drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

76

#define mmUVD_RBC_RB_CNTL 0x3da9

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

70

#define mmUVD_RBC_RB_CNTL 0x3DA9

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

74

#define mmUVD_RBC_RB_CNTL 0x3da9

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

80

#define mmUVD_RBC_RB_CNTL 0x3da9

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

96

#define mmUVD_RBC_RB_CNTL 0x3da9

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

204

#define mmUVD_RBC_RB_CNTL 0x05a9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

390

#define mmUVD_RBC_RB_CNTL 0x05a9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

690

#define mmUVD_RBC_RB_CNTL 0x0269

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

785

#define mmUVD_RBC_RB_CNTL 0x02de

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1169

#define mmUVD_RBC_RB_CNTL 0x02de