drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

90

#define mmUVD_PGFSM_CONFIG 0x38f8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

62

#define mmUVD_PGFSM_CONFIG 0x38F8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

88

#define mmUVD_PGFSM_CONFIG 0x38f8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

100

#define mmUVD_PGFSM_CONFIG 0x38c0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

116

#define mmUVD_PGFSM_CONFIG 0x38c0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

28

#define mmUVD_PGFSM_CONFIG 0x00c0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

380

#define mmUVD_PGFSM_CONFIG 0x0000

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

395

#define mmUVD_PGFSM_CONFIG 0x0000

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

663

#define mmUVD_PGFSM_CONFIG 0x0000