drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

59

#define mmUVD_MPC_SET_MUXB1 0x3d7c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

59

#define mmUVD_MPC_SET_MUXB1 0x3D7C

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

57

#define mmUVD_MPC_SET_MUXB1 0x3d7c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

63

#define mmUVD_MPC_SET_MUXB1 0x3d7c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

79

#define mmUVD_MPC_SET_MUXB1 0x3d7c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

172

#define mmUVD_MPC_SET_MUXB1 0x057c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

352

#define mmUVD_MPC_SET_MUXB1 0x057c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

602

#define mmUVD_MPC_SET_MUXB1 0x023c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

767

#define mmUVD_MPC_SET_MUXB1 0x02d1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1147

#define mmUVD_MPC_SET_MUXB1 0x02d1