drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

58

#define mmUVD_MPC_SET_MUXB0 0x3d7b

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

58

#define mmUVD_MPC_SET_MUXB0 0x3D7B

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

56

#define mmUVD_MPC_SET_MUXB0 0x3d7b

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

62

#define mmUVD_MPC_SET_MUXB0 0x3d7b

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

78

#define mmUVD_MPC_SET_MUXB0 0x3d7b

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

170

#define mmUVD_MPC_SET_MUXB0 0x057b

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

350

#define mmUVD_MPC_SET_MUXB0 0x057b

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

600

#define mmUVD_MPC_SET_MUXB0 0x023b

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

765

#define mmUVD_MPC_SET_MUXB0 0x02d0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1145

#define mmUVD_MPC_SET_MUXB0 0x02d0