drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

57

#define mmUVD_MPC_SET_MUXA1 0x3d7a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

57

#define mmUVD_MPC_SET_MUXA1 0x3D7A

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

55

#define mmUVD_MPC_SET_MUXA1 0x3d7a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

61

#define mmUVD_MPC_SET_MUXA1 0x3d7a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

77

#define mmUVD_MPC_SET_MUXA1 0x3d7a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

168

#define mmUVD_MPC_SET_MUXA1 0x057a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

348

#define mmUVD_MPC_SET_MUXA1 0x057a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

598

#define mmUVD_MPC_SET_MUXA1 0x023a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

763

#define mmUVD_MPC_SET_MUXA1 0x02cf

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1143

#define mmUVD_MPC_SET_MUXA1 0x02cf