drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

56

#define mmUVD_MPC_SET_MUXA0 0x3d79

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

56

#define mmUVD_MPC_SET_MUXA0 0x3D79

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

54

#define mmUVD_MPC_SET_MUXA0 0x3d79

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

60

#define mmUVD_MPC_SET_MUXA0 0x3d79

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

76

#define mmUVD_MPC_SET_MUXA0 0x3d79

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

166

#define mmUVD_MPC_SET_MUXA0 0x0579

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

346

#define mmUVD_MPC_SET_MUXA0 0x0579

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

596

#define mmUVD_MPC_SET_MUXA0 0x0239

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

761

#define mmUVD_MPC_SET_MUXA0 0x02ce

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1141

#define mmUVD_MPC_SET_MUXA0 0x02ce