drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

60

#define mmUVD_MPC_SET_MUX 0x3d7d

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

55

#define mmUVD_MPC_SET_MUX 0x3D7D

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

58

#define mmUVD_MPC_SET_MUX 0x3d7d

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

64

#define mmUVD_MPC_SET_MUX 0x3d7d

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

80

#define mmUVD_MPC_SET_MUX 0x3d7d

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

174

#define mmUVD_MPC_SET_MUX 0x057d

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

354

#define mmUVD_MPC_SET_MUX 0x057d

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

604

#define mmUVD_MPC_SET_MUX 0x023d

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

769

#define mmUVD_MPC_SET_MUX 0x02d2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1149

#define mmUVD_MPC_SET_MUX 0x02d2