drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

61

#define mmUVD_MPC_SET_ALU 0x3d7e

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

54

#define mmUVD_MPC_SET_ALU 0x3D7E

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

59

#define mmUVD_MPC_SET_ALU 0x3d7e

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

65

#define mmUVD_MPC_SET_ALU 0x3d7e

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

81

#define mmUVD_MPC_SET_ALU 0x3d7e

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

176

#define mmUVD_MPC_SET_ALU 0x057e

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

356

#define mmUVD_MPC_SET_ALU 0x057e

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

606

#define mmUVD_MPC_SET_ALU 0x023e

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

771

#define mmUVD_MPC_SET_ALU 0x02d3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1151

#define mmUVD_MPC_SET_ALU 0x02d3