drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

55

#define mmUVD_MPC_CNTL 0x3d77

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

53

#define mmUVD_MPC_CNTL 0x3D77

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

53

#define mmUVD_MPC_CNTL 0x3d77

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

59

#define mmUVD_MPC_CNTL 0x3d77

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

75

#define mmUVD_MPC_CNTL 0x3d77

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

344

#define mmUVD_MPC_CNTL 0x0577

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

592

#define mmUVD_MPC_CNTL 0x0237

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

757

#define mmUVD_MPC_CNTL 0x02cc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1137

#define mmUVD_MPC_CNTL 0x02cc